For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Quantum-well devices formed in epitaxially grown semiconductor hetero-structures, such as in III-V material systems, offer exceptionally high carrier mobility in the transistor channels due to low effective mass along with reduced impurity scattering by delta doping. These devices provide high drive current performance and appear promising for future low power, high speed logic applications.
One issue for quantum-well devices is the requirement that the quantum-well itself must be fairly thick (˜150 Angstroms) in order to maintain high mobility in a quantum-well device. A thick quantum-well results in a significant distance between the interior quantum-well interface and the centroid of an electron wave-function propagated in the quantum-well. This may lead to a detrimental increase in the effective electrical oxide thickness between the gate electrode and the wave-function center. However, thinner quantum-wells suffer from mobility degradation due to increased interface scattering since the electron wave-function is much closer to both interfaces in a thin quantum-well. In addition, thinning the quantum well can degrade mobility by allowing the wave-function to penetrate into the low mobility barrier material.